Chip circuito integrato

Circuiti integrati digitali serie 74

Circuiti integrati digitali serie CD40

Accoppiatori ottici

Orologio e calcolatrice di circuiti integrati

Amplificatori operazionali

Interruttore di accensione circuito integrato

Driver circuito integrato

Memoria flash

Memoria

Audio speciale

Clock/ Timing - Specifico per l'applicazione

Clock/ Timing - Drivers, buffer orologio

Clock/ Timing - Generatori orologio, PLL, sintetizzatori di frequenza

Clock/ Timing - Linee di ritardo

Clock/ Timing - Batterie circuito integrato

Clock/ Timing - Oscillatori e Timer programmabili

Clock/ Timing - Clock in Real Time

Acquisizione dati - ADC / DAC - Scopo speciale

Acquisizione dati - Front end analogico (AFE)

Acquisizione dati - Convertitore da analogico a digitale (ADC)

Acquisizione dati - Potenziometro digitale

Acquisizione dati - Convertitore da digitale ad analogico (ADC)

Acquisizione dati - Controller Touch-screen

Incorporato - CPLD (dispositivi logici programmabili complessi)

Incorporato - DSP ( processori segnali digitali)

Incorporato - FPGA ( dispositivi programmabili)

Incorporato - FPGA ( dispositivi programmabili) con microcontroller

Incorporato - Microcontroller, Microprocessori, Moduli FPGA

Incorporato - Microcontroller

Incorporato - Microcontroller - Specifica Applicazione

Incorporato - Microprocessori

Incorporato - PLD (dispositivo logico programmabile)

Incorporato - Sistema su chip (SoC)

Interfaccia - Interruttori analogici - Scopo speciale

Interfaccia - Interruttori analogici, multiplexer, demultiplexer

Interfaccia - CODEC

Interfaccia - Controller

Interfaccia - Sintesi digitale diretta (DSS)

Interfaccia - Driver, Ricevitori, Transceiver

Interfaccia - Codificatori, Decodificatori, Convertitori

Interfaccia - Filtri - Attivi

Interfaccia - Espansori I / O

Interfaccia - Modem - CI e moduli

Interfaccia - Moduli

Interfaccia - Interfacce sensore e rilevatore

Interfaccia - Sensore, Touch Capacitivo

Interfaccia - Serializzatori, Deserializzatori

Interfaccia - Buffer di segnale, Ripetitori, Splitter

Interfaccia - Terminatori di segnale

Interfaccia - Specializzato

Interfaccia - Telecom

Interfaccia - UART (Trasmettitore Asincrono Universale del Ricevitore)

Interfaccia - Registrazione e Riproduzione vocale

Lineare - Amplificatori - Audio

Lineari - Amplificatori - Strumentazione, Amplificatori operazionali, Amplificatori buffer

Linear - Amplificatore - Scopo speciale

Lineare - Amplificatore - Amplificatore Video e Moduli

Lineari - Moltiplicatori analogici, Divisori

Lineare - Comparatori

Lineare - Elaborazione video

Logica - Buffer, Driver, Ricevitori, Transceiver

Logica - Comparatori

Logica - Contatori, Divisori

Logica - Memoria FIFO

Logica - Flip Flops

Logica - Gate e Inverter

Logica - Gate e Inverter - Multifunzione, Configurabile

Logica - Latch

Logica - Multivibratori

Logica - Generatori e Controllori di parità

Logica - Registri a scorrimento

Logica - Interruttori di segnale, Multiplexer, Decodificatori

Logica - Logica speciale

Logica - Traduttori, Cambi di livello

Logica - Funzioni Bus Universale

Memoria - Batterie

Memoria - Proms di configurazione per FPGA

Memoria - Controller

PMIC - Convertitori ca-cc, Commutatori offline

PMIC - Caricabatterie

PMIC - Gestione della batteria

PMIC - Regolamentazione / Gestione attuale

PMIC - Driver di visualizzazione

PMIC - Misurazione dell'energia

PMIC - Driver full-half-bridge

PMIC - Drivers Gate

PMIC - Controller Hot Swap

PMIC - Driver laser

PMIC - Driver LED

PMIC - Illuminazione, Regolatori di zavorra

PMIC - Driver per motori, Controller

PMIC - Controller OR, Diodi ideali

PMIC - PFC (correzione del fattore di potenza)

PMIC - Interruttori di distribuzione dell'alimentazione, Driver di caricamento

PMIC - Power Management - Specializzato

PMIC - Controller Power Over Ethernet (PoE)

PMIC - Controller di alimentazione, Monitor

PMIC - Convertitori da RMS a CC

PMIC - Supervisori

PMIC - Gestione termica

PMIC - Convertitori V / F e F / V

PMIC - Riferimento di tensione

PMIC - Regolatori di tensione - Controllori a commutazione cc-cc

PMIC - Regolatori di tensione - Regolatori a commutazione cc-cc

PMIC - Regolatori di tensione - Lineari

PMIC - Regolatori di tensione - Lineari + commutazione

PMIC - Regolatori di tensione - Controllori regolatori lineari

PMIC - Regolatori di tensione - Scopo speciale

CI Specializzati

Moduli

IGBT

IPM

Tiristori

Raddrizzatori

Alimentazione elettrica

Modulo Smart Power

SCR, GTO e Diodo

FET

Transistor Darlington

Moduli RF

PRODOTTI CNC

CODIFICATORE

Motore

Servo Drive & Amplificatore & Servo

Modulo Diodo

Modulo Transistor

Relè di Commutazione

PLC

Invertitore

Contattore e Interruttore

Scheda Ascensore

Controllo Settore

Transistor

Diodo

Transistor bipolari

resistenze

Resistori a film di carbonio

Resistori di cemento

Resistori per montaggio su telaio

Resistore a chip - Montaggio superficiale

Resistori rilevatori di corrente

Resistore a chip fusibile

Resistori SMD ad alta precisione e bassa TCR

Resistori ad alta tensione

Resistori a strisce LED

Resistori MELF

Resistori in lega metallica

Resistori a film metallico (TH)

Resistori di smalto metallico

Resistori a film di ossido di metallo

Resistori all'ossido di metallo

Termistori NTC

Termistori PTC

Fotoresistenze

Potenziometri e resistori variabili

Potenziometro di precisione

Reti e array di resistori

Reti e array di resistori (TH)

Resistori Ultrabassi (SMD)

Resistori variabili

Varistori

Resistori ad avvolgimento

Condensatori

Condensatori elettrolitici in alluminio - SMD

Condensatore CL21

Condensatori a dischi ceramici

Condensatori ad alta tensione

Condensatore in film di poliestere metallizzato

Condensatori ceramici multistrato MLCC - Piombo

Condensatori ceramici multistrato MLCC - SMD&SMT

Condensatore di Mylar

Condensatori all'ossido di niobio

Condensatori a film di poliestere

Condensatore elettrolitico polimero solido

Supercondensatori e Ultracondensatori

Condensatori di soppressione

Condensatori al tantalio

Trimmer, condensatori variabili

Induttori e trasformatori di ferrite

Antenne

Trasformatori di correnti

Induttori Generali (TH)

Induttori HF

Induttori (SMD)

Filtro LINE

Induttori di potenza

Trasformatore di potenza

Trasformatore RJ45

Induttore radiale (TH)

Gli induttori circolari

Crystals

49S

49SMD

49U

Risonatori ceramici

Oscillatori DIP (XO)

Cristalli a cilindro radiale

Risuonatori SAW

Cristalli SMD

Oscillatori SMD (XO)

Connettori

Connettori AV

Connettori audio e video

Connettori a banana e punta

Connettori bordo scheda

Connettori circolari

Connettore - Prese per schede

Connettori

Connettori-Accessori

Connettori- Alloggiamenti

Contatti

Connettori D-Sub

Connettori Ethernet&Connettori modulari

Connettori FFC, FPC (flessibile piatto)

Connettori in fibra ottica

Prese per circuiti integrati e componenti

Tubi luminosi a LED

Connettori mezzanine (da scheda a scheda)

Connettori PCB - Basette, pin maschio

Connettori PCB - Basette, prese, prese femmina

Connettori PCB - Alloggiamenti

Connettori di alimentazione

Connettori RF&Connettori coassiali

Shunt e ponticelli

Morsettiere - Accessori

Morsettiere - Blocchi a barriera

Morsettiere - Din Rail, canale

Morsettiere - Basette, spine e prese

Terminali

Clip di prova

Punti di prova&anelli di prova

Connettori USB

Connettori non specificati

Cablaggio a vite

Cablaggio a molla

Morsettiere innestabili

Morsettiere passanti

Terminali automobilistici

Alloggiamenti terminali, guaine isolanti e blocchi

Connettori e terminali per cavi a scollegamento rapido

Utensili di ricambio e usura

Connettori automobilistici

Connettori PCB

Accesso

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il numero di prodotti correlati: 1807
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CD4040BM96

Enlarge

Original parts, guaranteed brand new

CD4040BM96

SOP

Texas Instruments

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

Utsource Original Store

≥3:

€0.44264

€0.39837

≥50:

€0.40575

€0.36517

≥100:

€0.36886

€0.33198

From: €0.36886

Stock:10000

Minimo:5

Preferito

SN74S163N

Enlarge

Used and refurbished parts guaranteed can work well

SN74S163N

DIP-16

Texas Instruments

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

Utsource

≥1:

€0.63234

€0.56910

≥5:

€0.47425

€0.42683

≥10:

€0.33197

€0.29878

≥20:

€0.31617

€0.28455

≥50:

€0.28455

€0.25610

≥100:

€0.27665

€0.24898

≥200:

€0.26874

€0.24187

≥500:

€0.26084

€0.23476

≥1000:

€0.25293

€0.22764

From: €0.25293

SN74S163N is a synchronous 4-bit binary counter with a synchronous reset produced by Texas Instruments. It is a 16-pin dual in-line package (DIP-16). Description: The SN74S163N is a synchronous 4-bit

Stock:10000

Minimo:4

Preferito

CD74ACT163M96E4

Enlarge

Original parts, guaranteed brand new

CD74ACT163M96E4

SOP16

TI Texas Instruments

1547+

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

Utsource Original Store

≥1:

€1.54796

€1.39317

≥5:

€1.16097

€1.04487

≥10:

€0.69658

€0.62692

≥20:

€0.67723

€0.60951

≥50:

€0.65788

€0.59210

≥100:

€0.63853

€0.57468

≥200:

€0.61918

€0.55727

≥500:

€0.61145

€0.55030

≥1000:

€0.59984

€0.53985

From: €0.59984

Description: The CD74ACT163M96E4 is a high-speed CMOS logic device from Texas Instruments. It is a 16-bit synchronous binary counter with an asynchronous reset. Features: High-speed CMOS logic 16-

Stock:10000

Minimo:5

Preferito

SN74HC163N

Enlarge

Used and refurbished parts guaranteed can work well

SN74HC163N

DIP-16

Texas Instruments

0230+

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Utsource

≥1:

€0.79042

€0.71138

≥5:

€0.59282

€0.53353

≥10:

€0.41498

€0.37348

≥20:

€0.39521

€0.35569

≥50:

€0.35569

€0.32012

≥100:

€0.34581

€0.31123

≥200:

€0.33593

€0.30234

≥500:

€0.32605

€0.29345

≥1000:

€0.31617

€0.28455

From: €0.31617

SN74HC163N is a synchronous 4-bit binary counter made by Texas Instruments. It is a 16-pin DIP package and is part of the 74HC logic family. Description: The SN74HC163N is a synchronous 4-bit binary

Stock:10000

Minimo:3

Preferito

74AC161PC

Enlarge

Used and refurbished parts guaranteed can work well

74AC161PC

DIP16

National Semiconductor

94+

Synchronous Presettable Binary Counter; Package: DIP; No of Pins: 16; Container: Rail

Utsource

≥1:

€3.10058

€2.79052

≥5:

€2.06705

€1.86035

≥10:

€1.86035

€1.67431

≥20:

€1.80867

€1.62781

≥50:

€1.75700

€1.58130

≥100:

€1.70532

€1.53479

≥200:

€1.65364

€1.48828

≥500:

€1.63297

€1.46968

≥1000:

€1.60197

€1.44177

From: €1.60197

Stock:10000

Minimo:2

Preferito

CD40192BE

Enlarge

Used and refurbished parts guaranteed can work well

CD40192BE

DIP-16

Ti/rca

CMOS PRESETTABLE UP/DOWN COUNTERS(DUAL CLOCK WITH RESET)

Utsource

≥1:

€2.89821

€2.60839

≥5:

€2.75330

€2.47797

≥10:

€2.60839

€2.34755

≥20:

€2.53593

€2.28234

≥50:

€2.46348

€2.21713

≥100:

€2.39103

€2.15193

≥200:

€2.31857

€2.08671

≥500:

€2.28959

€2.06063

≥1000:

€2.24611

€2.02150

From: €2.24611

Stock:10000

Minimo:1

Preferito

74ACT161PC

Enlarge

Original parts, guaranteed brand new

74ACT161PC

DIP

National Semiconductor

9312+

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

Utsource Original Store

≥1:

€0.46108

€0.41497

≥10:

€0.27665

€0.24898

From: €0.27665

Description: The 74ACT161PC is a high-speed 4-bit synchronous binary counter. Features: * High-speed operation * Synchronous counting * Asynchronous reset * Output capability: standard * Inputs are T

Stock:10000

Minimo:5

Preferito

CD40192BE

Enlarge

Original parts, guaranteed brand new

CD40192BE

DIP16

HLF

18+

IC UP/DOWN COUNTR PRESET 16-DIP

€0.23054

€0.20749

From: €0.23054

Stock:99999

Minimo:200

Preferito

SN74HC191N

Enlarge

Original parts, guaranteed brand new

SN74HC191N

DIP16

HLF

18+

IC 4-BIT UP/DN BIN CNTR 16-DIP

€0.26347

€0.23713

From: €0.26347

Stock:99999

Minimo:200

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74ACT163SCX

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Original parts, guaranteed brand new

74ACT163SCX

SOP16

FSC

06+ROHS

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

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€0.22132

€0.19919

≥100:

€0.20287

€0.18259

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€0.18443

€0.16599

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Description: 74ACT163SCX is a high-speed synchronous 4-bit binary counter with synchronous reset. Features: - High-speed synchronous operation - Synchronous reset - Fully static operation - Outputs s

Stock:10000

Minimo:10

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SN74HC193N

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Original parts, guaranteed brand new

SN74HC193N

DIP16

HLF

18+

IC 4-BIT UP/DOWN COUNTER 16-DIP

€0.26347

€0.23713

From: €0.26347

Stock:99999

Minimo:200

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74VHC393MTCX

Enlarge

Original parts, guaranteed brand new

74VHC393MTCX

TSSOP

Fairchild

1021+

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

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≥1:

€1.05390

€0.94851

≥5:

€0.79042

€0.71138

≥10:

€0.47425

€0.42683

≥20:

€0.46108

€0.41497

≥50:

€0.44791

€0.40312

≥100:

€0.43473

€0.39126

≥200:

€0.42156

€0.37940

≥500:

€0.41629

€0.37466

≥1000:

€0.40838

€0.36755

From: €0.40838

Description: The 74VHC393MTCX is a high-speed CMOS dual 4-stage binary ripple counter fabricated with silicon gate C2MOS technology. Features: High speed: tpd = 8.0ns (typ.) at VCC = 5V Low power d

Stock:10000

Minimo:2

Preferito

MM74HC393N

Enlarge

Original parts, guaranteed brand new

MM74HC393N

DIP14

National Semiconductor

2013+

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

Utsource Original Store

≥1:

€0.79042

€0.71138

≥5:

€0.59282

€0.53353

≥10:

€0.41497

€0.37347

≥20:

€0.39521

€0.35569

≥50:

€0.35569

€0.32012

≥100:

€0.34581

€0.31123

≥200:

€0.33593

€0.30234

≥500:

€0.32605

€0.29344

≥1000:

€0.31617

€0.28455

From: €0.31617

Description: The MM74HC393N is a high-speed CMOS 4-bit binary counter with dual clock. Features: High Speed Operation: tPD = 10 ns (TYP.) at VCC = 5 V Low Power Consumption: ICC = 1 μA (MAX) at Ta =

Stock:10000

Minimo:4

Preferito

SN74LS191N

Enlarge

Original parts, guaranteed brand new

SN74LS191N

DIP16

HLF

18+

IC SYNC UP/DOWN COUNTER 16-DIP

€0.26347

€0.23713

From: €0.26347

Description: 4-Bit Synchronous Up/Down Counter Features: - Synchronous operation - Counts up or down - Ripple carry output - Asynchronous master reset - Inputs and outputs fully buffered - Outp

Stock:98999

Minimo:200

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MC14029BCP

Enlarge

Used and refurbished parts guaranteed can work well

MC14029BCP

DIP-16

Motorola

99+

Binary/Decade Up/Down Counter

Utsource

≥1:

€1.10342

€0.99308

≥5:

€0.82757

€0.74481

≥10:

€0.49654

€0.44688

≥20:

€0.48275

€0.43448

≥50:

€0.46895

€0.42206

≥100:

€0.45516

€0.40964

≥200:

€0.44137

€0.39723

≥500:

€0.43585

€0.39227

≥1000:

€0.42757

€0.38482

From: €0.42757

Stock:10000

Minimo:2

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CD4060BCN

Enlarge

Used and refurbished parts guaranteed can work well

CD4060BCN

DIP-16

National Semiconductor

95+

14-Stage Ripple Carry Binary Counters; Package: DIP; No of Pins: 16; Container: Rail

Utsource

≥1:

€0.64184

€0.57766

≥5:

€0.48138

€0.43324

≥10:

€0.33697

€0.30327

≥20:

€0.32092

€0.28883

≥50:

€0.28883

€0.25995

≥100:

€0.28081

€0.25273

≥200:

€0.27278

€0.24550

≥500:

€0.26476

€0.23828

≥1000:

€0.25674

€0.23107

From: €0.25674

Description: The CD4060BCN is a CMOS 14-stage ripple carry binary counter/divider and oscillator. Features: - High speed operation - Low power consumption - High noise immunity - High output drive ca

Stock:10000

Minimo:4

Preferito

CD4020BCM

Enlarge

Original parts, guaranteed brand new

CD4020BCM

SOP

FAI

99+

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

Utsource Original Store

≥3:

€0.44264

€0.39837

≥50:

€0.40575

€0.36517

≥100:

€0.36886

€0.33198

From: €0.36886

Description: The CD4020BCM is a 14-stage ripple-carry binary counter/divider and oscillator. Features: High Speed Operation Low Power Consumption Wide Operating Temperature Range Low Input

Stock:10000

Minimo:5

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74F160APC

Enlarge

Used and refurbished parts guaranteed can work well

74F160APC

DIP-16

FSC

00+

Utsource

≥1:

€1.97606

€1.77845

≥5:

€1.31737

€1.18563

≥10:

€1.18563

€1.06707

≥20:

€1.15270

€1.03743

≥50:

€1.11976

€1.00779

≥100:

€1.08682

€0.97814

≥200:

€1.05390

€0.94851

≥500:

€1.04072

€0.93665

≥1000:

€1.02097

€0.91887

From: €1.02097

Stock:10000

Minimo:2

Preferito

CD4040BCN

Enlarge

Original parts, guaranteed brand new

CD4040BCN

DIP

Fairchild

9824+

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

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≥1:

€2.37127

€2.13414

≥5:

€1.58084

€1.42276

≥10:

€1.42276

€1.28048

≥20:

€1.38324

€1.24491

≥50:

€1.34372

€1.20935

≥100:

€1.30420

€1.17378

≥200:

€1.26468

€1.13821

≥500:

€1.24887

€1.12398

≥1000:

€1.22515

€1.10264

From: €1.22515

Description: The CD4040BCN is a CMOS 12-stage ripple carry binary counter/divider and oscillator. Features: High speed operation Low power consumption High noise immunity High output drive capabi

Stock:10000

Minimo:2

Preferito

SN74HC161N

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Original parts, guaranteed brand new

SN74HC161N

DIP16

HLF

18+

IC 4-BIT BINARY COUNTER 16-DIP

€0.23054

€0.20749

From: €0.23054

Stock:99999

Minimo:200

Preferito

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